1. Field of the Invention
The present invention relates to a lead frame, a semiconductor chip package, and a method of manufacturing the semiconductor chip package. More particularly, the present invention relates to a lead frame, a semiconductor chip package using the lead frame and having an exposed lead frame package (ELP) structure, in which the thickness of the semiconductor chip package is reduced due to the use of the lead frame, and a method of manufacturing the same.
2. Description of the Related Art
Quad flat packaging (QFP) and ball grid array (BGA) packaging techniques may be used when manufacturing semiconductor packages, to electrically and electronically connect a semiconductor chip to an external environment.
A lead frame may be used in manufacturing a QFP. The lead frame may not only serve to provide functions performed by a semiconductor chip to an external circuit through electrically connecting the semiconductor chip to the external circuit, but may also physically support the semiconductor chip.
The lead frame may include a die pad, on which the semiconductor chip may be mounted leads, which may be wire-bonded to chip pads on the semiconductor chip, and a frame, which may support the die pad and the leads.
A QFP generally may have an exposed lead frame package (ELP) structure. A part of a lead frame may be exposed on the outside of a body of the package. In particular, in a QFP with an ELP structure, the die pad and the lower parts of the leads may be exposed to a bottom surface of the body of the package.
A conventional semiconductor chip package may be explained with reference to FIGS. 10 and 11.
FIG. 10 illustrates a plan view of a conventional semiconductor chip package and FIG. 11 illustrates a cross-sectional view taken along a line XI-XI′ of FIG. 10.
As illustrated in FIGS. 10 and 11, the semiconductor chip package according to the conventional semiconductor chip package may include a lead frame, a semiconductor chip 50, bonding wires 60, and an encapsulant 70, which may be used in a molding process. The lead frame may include a plurality of leads 10, which may be formed along four sides of the lead frame, a die pad 20, which may be formed in the middle of the lead frame, and tie bars 30, which may extend from the edge of each of the four sides and may be connected to the die pad 20.
An upper surface of the semiconductor chip 50 may be an active surface, on which a plurality of chip pads 51 may be formed, and a lower surface, which may be a non-active surface, may be adhered to an upper part of the die pad 20.
The bonding wires 60 may electrically connect the plurality of chip pads 51 with the plurality of leads 10.
The encapsulant 70 may be formed to encapsulate the semiconductor chip 50 and the bonding wires 60. Bonding portions of the bonding wires 60 may be formed by a molding method using a die. In addition, the bonding portions may be made of an insulating material. Lower surfaces of the plurality of leads 10 (the leads may be completely encapsulated by 70 as illustrated in FIG. 11) and a lower surface of the die pad 20 may not be encapsulated by the encapsulant 70 and may be exposed outside the package.
The semiconductor chip 50 may be mounted on the die pad 20. Because the semiconductor chip 50 may be located on an upper part of the die pad 20, the lengths of the bonding wires 60 connecting the semiconductor chip 50 to the leads 10 may be at least as long as a thickness of the semiconductor chip 50. Thus, electrical characteristics such as high connection resistance may be reduced.
To solve the problems described above, the tie bars 30 and the die pad 20 may be bent downward (as referred to as, down-set) and the semiconductor chip 50 may be adhered to the upper part of the down-set die pad 20 so that the lengths of the bonding wires 60 may be reduced or minimized.
However, the above structure of the package may have a limitation in adjusting the thickness of the package.
Thus, conventionally, the semiconductor chip may have been constructed to have a smaller thickness in order to reduce or minimize the thickness of the semiconductor chip package.
However, as the semiconductor chip is reduced, a wafer may be easily broken during a wafer handling process. As a result, a sawing device for cutting the wafer may not be used.
Further, after manufacturing of the package is complete, the weakened semiconductor chip may be prone to damage by even a small impact.